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With regard to high speed design rules, my first rule of thumb is to be cautious about rules of thumb. I use rules of thumb as an early estimate that helps me to get an idea of how all of my design rules and goals play together.
But there is a bigger power authority across the border, the North American Electric Reliability Council (NERC).
There are many 1502s on fleabay, but rarely do you see a working example. They have a strange PSU that requires functional NiCd batteries, some caps can leak and destroy PCB traces, and the tunnel diode can be damaged by any external voltage – hence the special shorting BNC connector. But if you can find a working example, they can give useful results and the vintage sampling scope can be hypnotic to watch.
Transformer explosions, for instance, happen often enough — sometimes multiple times a year — that utilities use specialized walls to separate large power transformers from each other to prevent cascading failures, he noted.
Behind the technology is a fast rise time pulse. I had actually started to write this post as instructions on how to make a fast rise time generator using various techniques after reading Jenny List’s article on pulse edges. During my research I bought a pulse generator that clocked in at 32 picosecond (ps) rise time (sold as 40ps or faster) designed by an engineer named Leo Bodnar. When I received my pulse generator I saw that Leo had used a venerable piece of equipment known as the Tek CSA803/SD24 Communications Signal Analyzer (CSA) which has a 20Ghz bandwidth and a 17.5 ps rise time pulse to characterize my module. I just had to have one of these CSA’s myself and watching eBay got me a good find, though I haven’t told my wife yet. With this new-to-me piece of equipment I set off to test how easily I could see the effects of the glass fiber direction on impedance.
Yes, my opinion is it is that sampling head and it’s bandwidth is where the magic juju is. My SD-24 cost almost as much as the CAS frame, but well worth it given in included the pulse generator also, and the backplane trigger path. They have a 50ghz head that I drooled over that I don’t need, but I drooled none the less.
We know the capacitance of the area of the metal since we are talking about 50Ω impedance in general. Per the equations above a 6mil trace would have an additional capacitance of 9.6fF (femtofarad), or 0.0000000096 μF, this is really small. The other thing that minimizes the effect of the corner is just how fast it goes by at the velocities we are talking about, which are sizable fractions of the speed of light. Given that a signal travels 6 inches in 1ns on a standard FR4 PCB, the signal will get through the corner in 30ps. (Which is why I have to use equipment with a 17.5ps rise time to examine it)
Metal film also starts at a lower tolerance, 0.1%. They also have good noise characteristics, low non-linearity and good long-term stability plus a wide range of uses.
The growing criticism of inline inductors is why put a low pass filter in line with a component with high speed current needs. It may reduce the symptom but by starving the part of current when the real issue is that a lower impedance power supply is needed. A PDN with no inductance and unlimited current would not need a ferrite, so how to get there in real life is the challenge. With that said, ferrites are still great for stripping noise off signals headed for the connectors, etc.
Combining the flexibility of a FPGA with the performance and cost benefits of an SoC is pushing this technology well into the mainstream.
It's not a perfect fit—but it's close enough for me. Clearly, I could play around with the parameters a bit to get a better fit but I think this shows that my model isn't crazy.
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